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All the Perl that's Practical to Extract and Report

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  • by spur (4197) on 2005.05.31 10:44 (#40810) Homepage
    VHDL's generate construct (and the "for" loop used in processes) is not only for module instantiations. It's indeed capable of making what you demonstrated.

    Anyhow, as a hardware engineer I find Perl very useful - it's automating a lot of tasks for me - including HDL code generation. When it comes to us logic designers / embedded engineers, Perl is one of the most useful and respected languages.