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agent (5836)

agent
  agentzh@yahoo.cn
http://agentzh.spaces.live.com/

Agent Zhang (章亦春) is a happy Yahoo! China guy who loves Perl more than anything else.

Journal of agent (5836)

Monday May 30, 2005
10:27 PM

Regard Perl6 as a Super HDL

[ #24954 ]

=from 2005.5.31.8:00.AM
=to ...5.31.8:45.AM

In hardware design, it is sometimes desirable to depict the logic circuit diagrams in a constructive manner, just like the way we build a complex data structure using a general-purpose programming language. For example, we might wish to express a cascaded connection of 32 full adders, which is known as a 32-bit carry-ripple adder, by the following pseudo code (I borrowed Perl6 syntax here to illustrate the idea):

        my @adders;
        for (0..31) -> $i {
                push @adders, FA.new(
                        name => "cell$i",
                        X => "x[$i]", Y => "y[$i]", Cin => "c[$i]",
                        S => "s[$i]", Cout => "c[" ~ ($i+1) ~ "]"
                );
        }

Unfortunately, so far as I know, earlier versions of Verilog HDL lack the ability to construct such things effectively, so a lot of typing is necessary if we use pure Verilog.

Is there a way to use Perl6 syntax directly as an HDL? The answer is certainly "yes". The simplest solution may be as follows:

  • Write Perl6 codes just like the example we gave above using a predefined class library
  • Run this script and generate corresponding Verilog codes.

In the preceding example, we might write a Perl6 program named adder32.p6, which probably prints out something like the following:

        module adder32(x, y, c_in, c_out, s);
                input [31:0] x, y;
                input c_in;
                output c_out;
                output [31:0] s;
                wire [32:0] c;
                assign c_out = c[32];
                assign c[0] = c_in;

                FA cell0 (.X(x[0]), .Y(y[0]), .Cin(c[0]), .S(s[0]), .Cout(c[1]));
                FA cell1 (.X(x[1]), .Y(y[1]), .Cin(c[1]), .S(s[1]), .Cout(c[2]));
                FA cell2 (.X(x[2]), .Y(y[2]), .Cin(c[2]), .S(s[2]), .Cout(c[3])); // an awful lot omitted here...
                FA cell30 (.X(x[30]), .Y(y[30]), .Cin(c[30]), .S(s[30]), .Cout(c[31]));
                FA cell31 (.X(x[31]), .Y(y[31]), .Cin(c[31]), .S(s[31]), .Cout(c[32]));
        endmodule

The code generation details can be encapsulated into the basic Perl6 library, thus becoming transparent to EDA designers. Some template-driven code generators, such as Perl Template Toolkit, are equally helpful.

It is worth noting that the generate construct provided by VHDL and Verilog-2001 can build the 32-bit carry-ripple adder in our example by virtue of loops as well. However, at this moment, they seem to be only applicable to module instantiations. So we can expect the code generation solution based on Perl to have a great future.

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  • VHDL's generate construct (and the "for" loop used in processes) is not only for module instantiations. It's indeed capable of making what you demonstrated.

    Anyhow, as a hardware engineer I find Perl very useful - it's automating a lot of tasks for me - including HDL code generation. When it comes to us logic designers / embedded engineers, Perl is one of the most useful and respected languages.