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agent (5836)


Agent Zhang (章亦春) is a happy Yahoo! China guy who loves Perl more than anything else.

Journal of agent (5836)

Monday May 23, 2005
04:49 AM

Make a Computer of My Own

[ #24830 ]

=from 2005.5.23.7:50.AM
=to ...5.23.9:05.AM

The two weeks' efforts on summarizing Carl's "Computer Organization" have been proved fruitful. Now I've got some insight into the internals of computer systems. Maybe it's time for me to *make* a quite complete computer of my own. This idea seems to be a little insane at the first glance; however, it has been one of my goals since high school.

The current plan is as follows:

  1. Use standard Verilog HDL to implement the processor, the system bus, RAMs, caches, DMA controllers and some basic I/O device interfaces.
  2. Test the Verilog design in commercial simulators and synthesizers, such as Altera Quartus II and ModelSim.
  3. Implement a simple Verilog compiler that can convert the Verilog source to my Tesla HDL codes.
  4. Perform real-time simulation by virtue of my Tesla simulator developed in last term.
  5. Program the well-tested design down to the devices, such as FPGA, finishing the whole process.

The step of developing a Verilog compiler may be unnecessary. Transforming the netlist generated by other people's Verilog compiler to Tesla code seems to be much more straightforward. Fortunately, the meta netlist (.vqm file) output by Quartus II is very similar to Verilog syntax, though a little odd. I wonder if there are any specifications for this format.

In fact, if there's a real-time simulator already available on the web, the steps 3 and 4 can be completely bypassed. I'm guessing the FLI (Foreign Language Interfaces) provided by ModelSim may be the right place to look at.

However, I still believe that it is doubtless more interesting and more challenging to simulate my design in my own simulator, Tesla, because all the boring principles and algorithms I learned from the course on Logic Design will get an opportunity to be applied to real lift. Yeah, every student has a dream to act as a "practicing theorist".

Verilog is very concise compared to VHDL, so it's an ideal language to describe large designs. I can't understand why our university chose VHDL in all our hardware courses. Weird.

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